Boards Archives - EDU Market

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Boards Archives - EDU Market https://edu-market.net/product-category/engineering/fpga/boards/ Educational Labs & Instruments Fri, 22 Nov 2024 15:41:50 +0000 en-US hourly 1 https://wordpress.org/?v=6.9.4 https://edu-market.net/wp-content/uploads/2023/02/Faveicon-64x62.png Boards Archives - EDU Market https://edu-market.net/product-category/engineering/fpga/boards/ 32 32 DE25-Standard Development Kit https://edu-market.net/everything/de25-standard-development-kit/ Mon, 18 Nov 2024 08:10:53 +0000 https://edu-market.net/?post_type=product&p=6470 DE25-Standard - The newest generation dev. kit for Altera ^® University Program!

Designed to address the applications requirements for digital logics, embedded systems, and robotics, the DE25-Standard development kit takes advantage of the Altera^® Agilex™ 5 SoC FPGA with 138K LEs to deliver 2.5x performance breakthrough and advanced feature sets such as 1GB DDR4 32-bit data bus, 64MB SDRAM, 8-channel ADC header, GPIO header, an HSMC high-speed connector, and black and light mini LCD, etc. A rich set of input and output features, such as robust switches, LEDs, seven-segment displays, and commonly-used I / O interfaces are included to meet the needs of teaching and experiments.

In addition, the DE25-Standard is armed with the advanced HDMI output port (1080P), a two-lane MIPI CSI / DSI connector for camera and display, and a composite RCA jack for surveillance camera. Developers can leverage the AI tensor block on the Agilex™ 5 FPGA, the MIPI CSI / DSI connector, HDMI output, and the composite RCA jack on the DE25-Standard to develop AI-related applications such as video processing and computer vision.

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]]>

DE25-Standard

FPGA: A5ED013BB32AE4S (138K LEs)
Dimension: 166 mm x 130 mm
Onboard USB-Blaster II
Support ASx4 Configure Mode with 128Mbits QSPI Flash
Board Management System
- Power Monitor
- Temperature Monitor
- Auto fan Control
Optional Active Heatsink

FPGA side

DDR4: 1GB DDR4 with 32-bit data bus (no ECC), shared with HPS.
SDRAM: 64MB SDRAM with 32-bit data bus (no ECC).
HDMI 1.4 Output Port (Support 1080P)
One 2-lanes MIPI Connector for Camera/Display
Composite video-In
24-bits audio codec: MIC-In, Line-In, and Line-Out
8-channel ADC with 2×5 header
IR TX/RX
One 3.3V 2×20 DE-GPIO Header
One HSMC connector with 4 transceivers.
User LED x10, Button x4, Slide Switch x10, 7-segment x6

HPS side

MicroSD Socket
DDR4: 1GB DDR4 with 32-bit data bus (no ECC), shared with FPGA
Gigabit Ethernet PHY + RJ45
Two USB Host ports with USB Type-A connector
UART to USB Port
128×64 LCD
Accelerometer
LED x1, Button x1, Cold Reset Button
One 3.3V 1×6 GPIO Header

Software Support

FPGA Example Code
Linux BSP

Block Diagram

Connection to 2×20 GPIO Daugher Card

Connect LT24

Connect MTL2

Connect D8M

Connect SMK

Connect RFS2

Connection to HSMC Daugher Card

Connect HTG

Connect ADA

Connect DCC

Size：166*130 mm

DE25-Standard Board
Type-C USB Cable
AC Power Cord
12V 60W Power Supply
Quick Start Guide
Four Silicon Footstands
Fan (Installed)

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]]> Atum A5 Development Kit https://edu-market.net/everything/atum-a5-development-kit/ Tue, 05 Nov 2024 04:44:02 +0000 https://edu-market.net/?post_type=product&p=6290 The Atum A5 Development Kit is Terasic’s first development kit in the Intel^® Agilex™ 5 FPGA portfolio. Powered by the largest Agilex^® 5 SoC FPGA with 656K LEs, the Atum A5 Development Kit is an out-of-the-box platform for advanced AI and vision application development.

With a rich set of interfaces ranging from 2.5G Ethernet, high-speed DDR4, QSFP+, PCIe Gen 3x4, FMC+ connectors, to MIPI connector and HDMI, the Atum A5 excels in a wide range of applications, including industrial networking, AI, embedded vision, medical and healthcare, video applications, and various other I/O expansion and high-speed applications!

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]]> Specifications

Atum A5 System Side

FPGA: A5ED065BB32AE4SR0 (656K LEs)
Dimension: 155 mm x 160 mm
Onboard USB-Blaster II
Support ASx4 Configure Mode with 512Mbits QSPI Flash
Active Heatsink
Board Management System
◦ Power Monitor
◦ Temperature Monitor
◦ Auto Fan Control

FPGA Side

HDMI Output Port (Support 1080P)
DDR4-A: 4GB DDR4 with 32-bit data bus (no ECC). Shared with HPS
DDR4-B: 4GB DDR4 with 32-bit data bus (no ECC)
One FMC+ connector with 16 transceivers
One 2.5G Ethernet PHY + RJ45
One QSFP+ Port for 40 GbE network interface
Two 2-lanes MIPI Connector for Camera/Display
One PCIe Calbing Gen3 x4 Socket
One 3.3V 2×20 DE-GPIO Header
One 3.3V 2×6 TMD Header
User LED x4, Button x4, DIP Switch x4

HPS Side

MicroSD Socket and 8GB eMMC
DDR4-A: 4GB DDR4 with 32-bit data bus (no ECC). Shared with FPGA
Gigabit Ethernet PHY + RJ45
USB 3.1 Gen1 (5Gbps; use 1 transceiver) with USB Type-C connector
UART to USB Port
LED x1, Button x1, Cold Reset Button
One 3.3V 2×6 GPIO Header. Including One I2C Bus

Software Support

FPGA Example Code
Linux BSP

Block Diagram

Connection to FMC Daughter Card

Connect to HDMI-FMC Daughter Card:

Connect to XTS-FMC Daughter Card:

Connect to 12G SDI-FMC Daughter Card:

Connection to MIPI Module

Connection to MIPI CSI-2 Camera Module:

Layout

TOP:

Board Size

Kit Content

Atum A5 Board
Active Heatsink (Installed)
MicroSD Card (Installed) + Card Reader
Type-C USB Cable
AC Power Cord
12V/10A 120W Power Supply
Quick Start Guide

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]]> DE1-SoC Board https://edu-market.net/everything/de1-soc-board/ Tue, 05 Nov 2024 04:35:51 +0000 https://edu-market.net/?post_type=product&p=6280 The DE1-SoC Development Kit presents a robust hardware design platform built around the Altera System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The DE1-SoC development board includes hardware such as high-speed DDR3 memory, video and audio capabilities, Ethernet networking, and much more.
The DE1-SOC Development Kit contains all components needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later ( 64-bit OS and Quartus II 64-bit are required to compile projects for DE1-SoC ).

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]]> Specifications

The DE1-SoC board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects.

The following hardware is provided on the board:

FPGA Device

Cyclone V SoC 5CSEMA5F31C6 Device
Dual-core ARM Cortex-A9 (HPS)
85K Programmable Logic Elements
4,450 Kbits embedded memory
6 Fractional PLLs
2 Hard Memory Controllers

Configuration and Debug

Serial Configuration device – EPCS128 on FPGA
On-Board USB Blaster II (Normal type B USB connector)

Memory Device

64MB (32Mx16) SDRAM on FPGA
1GB (2x256Mx16) DDR3 SDRAM on HPS
Micro SD Card Socket on HPS

Communication

Two USB 2.0 Host Ports (ULPI interface with USB type A connector) on HPS
UART to USB (USB Mini B connector)
10/100/1000 Ethernet
PS/2 mouse/keyboard
IR Emitter/Receiver

Connectors

Two 40-pin Expansion Headers (voltage levels: 3.3V)
One 10-pin ADC Input Header
One LTC connector (One Serial Peripheral Interface (SPI) Master ,one I2C and one GPIO interface )

Display

24-bit VGA DAC

Audio

24-bit CODEC, Line-in, line-out, and microphone-in jacks

Video Input

TV Decoder (NTSC/PAL/SECAM) and TV-in connector

ADC

sample rate: 500 KSPS
Channel number: 8
Resolution: 12 bits
Analog input range : 0 ~ 4.096 V

Switches, Buttons and Indicators

4 User Keys (FPGA x4)
10 User switches (FPGA x10)
11 User LEDs (FPGA x10 ; HPS x 1)
2 HPS Reset Buttons (HPS_RST_n and HPS_WARM_RST_n)
Six 7-segment displays

Sensors

G-Sensor on HPS

Power

12V DC input

Block Diagram of the DE1-SOC Board

Layout

Size：166*130 mm

Resources

Reference Book:

Modern Digital Designs with EDA, VHDL and FPGA

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]]> Developer Kit for OpenVINO™ Toolkit https://edu-market.net/everything/developer-kit-for-openvino-toolkit/ Tue, 05 Nov 2024 04:05:48 +0000 https://edu-market.net/?post_type=product&p=6272 Developer Kit for OpenVINO ™ Toolkit is a PCIe based FPGA card with high performance and competitive cost. It's equipped with the largest Cyclone V GT（or GX）device at 301K LE and it supports PCIe Gen 2 x4(GX device will support PCIe Gen 1 x4). The board comes with 1GB DDR3, 64MB SDRAM, UART-to-USB interface, and extension headers such as GPIO and Arduino. This makes Starter Platform for OpenVINO ™ Toolkit a re-configurable platform with adequate computing performance and low power consumption.

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]]> The package of Developer Kit for OpenVINO

Toolkit includes reference designs for all the peripherals onboard. It also has a detailed user manual for developers to follow and start building up a system according to their needs immediately.

The Developer Kit for OpenVINO Toolkit is a perfect starting point as OpenCL HPC (High Performance Computing) development platform. It supports Intel FPGA OpenCL BSP for developers to design a system with high level programming language. The computation demanding tasks can be off-loaded from CPU to FPGA, resulting in significant system performance improvement.

Specifications

CPU System:

CPU: Celeron Dual Core
Memory:
- 32GB eMMC
- 4GB DDR4
Interface
- Mini PCIe
- Ethernet
- HDMI
- UART
- USB
Power Input: 5V DC

FPGA System:

FPGA: Cyclone V 301K LE
Memory
- EPCQ256
- 64MB SDRAM
- 1GB DDR3 SDRAM
Communication
- UART to USB
- GT device supports PCIe Gen2 x4 (GX device supports PCIe Gen1 x4)
Expansion IO:
- Two 2×40 Expansion IO
- Arduino Uno Revision 3 Expansion Header
- SMA In/Out
On-Board USB Blaster
Power Input : 12V DC
LED/7-Segment/Button/Switch

Block Diagram of FPGA System

Layout

Resources

OpenVINO Development Guide – Download

Developer Kit for OpenVINO Toolkit Quick Start Guide – Download

Kit Contents

Developer Kit for OpenVINO Toolkit
USB 3.0 Cable for PCIe Conversion (Installed)
Mini USB Cable (installed)
12V Power Supply (for FPGA Board)
5V power Supply (for PC system)

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]]> DE10-Pro https://edu-market.net/everything/de10-pro/ Mon, 28 Aug 2023 13:11:21 +0000 https://edu-market.net/?post_type=product&p=4026 Inspired by the demands of AI, Data Center, and High-Performance Computing, DE10-Pro • FPGA-027 is purpose-built for acceleration and high-speed connectivity applications to address the demands of the next-generation high-performance systems.

The board itself takes advantage of the latest Intel® Stratix® 10 to obtain speed and power breakthrough (with up to 70% lower power). Also, armed with 32GB DDR4 memory module running at over 150 Gbps, up to 15.754 GB/s data transfer via PCIe Gen 3 x16 edge between FPGA and host PC, and 4 on-board QSFP28 (100GbE) connectors, the board delivers more than 2X the performance of previous generation acceleration cards.

DE10-Pro • FPGA-027 fully supports Intel Open VINO™ toolkit to provide optimal Computer Vision and Deep Learning solutions. Our clients' systems can achieve highest computing performance and lowest cost for their AI applications by leveraging the Stratix® 10 FPGA on DE10-Pro .

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]]> Features of the DE10-Pro :

FPGA
Intel Stratix 10 GX/SX FPGA
FPGA Configuration
On-Board USB Blaster II or JTAG header for FPGA programming
Avalon-ST (AVST x8) configuration via MAX V CPLD and CFI flash memory
ASx4 Configuration
Memory
128MB FLASH
Up to 8 GB DDR4 2666/2400(FPGA Core Speed 1/2 FPGA) for each socket
Communication and Expansion
Four QSFP28 connectors for 100/40/25/10 GbE network interface
PCI Express Gen3 x16 edge connector (includes PCIe drivers)
2×5 Timing expansion header
Others
General user input / output:
• 4 LEDs
• 2 push-buttons
• 2 slide switches
• U.FL clock input / output
On-Board Clock
• 50MHz Oscillator
• Programmable Clock Generator
System Monitor and Control
• Temperature sensor
• Power Monitor
• Fan control
Power
• PCI Express 2×4 power connector for 12V DC Input
• PCI Express edge connector power
Mechanical Specification
• PCI Express standard height and 3/4-length
Supported Memory Modules for Sockets
• DDR4-2666/2400 for FPGA Core Speed 1/2 FPGA
• QDRII+ 550MHz 144MBits
• QDRIV 1066MHz 144MBits

Download Datasheet for DE10-Pro • FPGA-027

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]]> Starter Platform for OpenVINO™ Toolkit https://edu-market.net/everything/starter-platform-for-openvino-toolkit/ Mon, 28 Aug 2023 13:02:45 +0000 https://edu-market.net/?post_type=product&p=4022 Starter Platform for OpenVINO™ Toolkit is a PCIe based FPGA card with high performance and competitive cost. It's equipped with the largest Cyclone V GT (or GX) device at 301K LE, and it supports PCIe Gen 2 x4(GX device will support PCIe Gen 1 x4). The board comes with 1GB DDR3, 64MB SDRAM, UART-to-USB interface, and extension headers such as GPIO and Arduino. This makes Starter Platform for OpenVINO™ Toolkit a re-configurable platform with adequate computing performance and low power consumption.

The package of Starter Platform for OpenVINO™ Toolkit includes reference designs for all the peripherals onboard. It also has a detailed user manual for developers to follow and start building up a system according to their needs immediately.

The Starter Platform for OpenVINO™ Toolkit is a perfect starting point as OpenCL HPC (High Performance Computing) development platform. It supports Intel FPGA OpenCL BSP for developers to design a system with high level programming language. The computation demanding tasks can be off-loaded from CPU to FPGA, resulting in significant system performance improvement.

The post Starter Platform for OpenVINO™ Toolkit appeared first on EDU Market.

]]> Features of the Starter Platform for OpenVINO Toolkit

FPGA Device
Cyclone V
• 301K Programmable Logic Elements
• 13,917 Kbits embedded memory
• Eight Fractional PLLs
• Two Hard Memory Controllers
• Nine Transceivers (the GT speed is 6.144G, and GX speed is 3.125G )
Configuration and Debug
• Quad Serial Configuration device-EPCQ256
• On-Board USB Blaster II (Mini-B USB connector)
Memory Device
• 64MB (32M x16) SDRAM
• 1GB (2 x256M x16) DDR3 SDRAM
Communication
• UART to USB（Mini-B USB connector）
• GT device supports PCIe Gen2x 4(GX device supports PCIe Gen1x 4)
Expansion I/O
2 x40 GPIO Header
• 36 General GPIO Pins
• Support 8 pairs LVDS TX and 8 pairs LVDS RX
• Diode protection circuit
• Configurable I/O standards: 1.5/1.8/2.5/3.3V
One Arduino Uno Revision 3 Expansion Header
Analog ADC
• SPI Interface
• 500Ksps Sampling Rate
• Eight Channels
• Analog Input Range：0 ~ 4.096 V
• Resolution: 12-bit
Digital IO
• Diode protection circuit
SMA IN/OUT 3.3V single port
Switches, Buttons, LED, and 7-Segments
• 5 User Buttons (4 normal buttons, one CPU_RESET_n)
• 4 User Switches
• 4 LEDs
• 2 7-Segments
Power
• 12V DC input
• PCIe 12V Input
Cooling
• 12V, 5000 Speed Fan

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]]> DE10-Agilex https://edu-market.net/everything/de10-agilex/ Mon, 28 Aug 2023 12:48:23 +0000 https://edu-market.net/?post_type=product&p=4018 Targeting the compute and acceleration needs from the edge to the core to the cloud, Terasic’s DE10-Agilex accelerator is purpose-designed to meet the ever-increasing demands for acceleration, compute, and fast data movement.

DE10-Agilex is based on the powerful Intel® Agilex™ FPGA to obtain speed and power breakthrough, with 40% higher performance, 40% lower power for equivalent performance. The accelerator includes PCI Express Gen 4.0 x16, two 200G QSFP-DD connectors and offers 32GB of DDR4 up to 680Gbps bandwidth to provide adaptable acceleration, maximum throughput and highly customizable processing of data for compute intensive applications.

DE10-Agilex • FPGA-025 fully supports Intel® OpenCL™ BSP and Intel® oneAPI Toolkits to provide optimal Computer Vision and Deep Learning solutions. Our clients' systems can achieve highest computing performance and lowest cost for their Data Center and AI applications by leveraging the Agilex® FPGA on DE10-Agilex accelerator.

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]]> Features of the DE10-Agilex

FPGA
Intel® Agilex FPGA AGFB014R24B2E2V
(FPGA with higher core speed is available, please contact Sales Team at sales@terasic.com for details.)
FPGA Configuration
On-Board USB Blaster II or JTAG header for FPGA programming
Avalon-ST (AVST x16) configuration via MAX 10 and CFI flash memory
Memory
128MB FLASH
Total 32GB DDR4 SODIMM with ECC.
Communication and Expansion
Two QSFPDD connectors for 200/100/40/25/10 GbE network interface
PCI Express Gen4 x16 edge connector (includes PCIe drivers)
2×5 Timing expansion header
UART
Others
General user input / output:
• 8 LEDs
• 2 push-buttons
• 2 slide switches
• U.FL clock input / output
On-Board Clock:
• 50MHz Oscillator
• Programmable Clock Generator ±5 ppb, 30.72MHz, OCXO ClocK (DNI)
System Monitor and Control:
• Temperature sensor
• Power Monitor
• Auto Fan control
• Auto Shutdown Control
Power In:
• PCI Express 2×4 power connector for 12V DC Input
• PCI Express edge connector power
Mechanical Specification:
• PCI Express standard height and 3/4-length
Supported Memory Modules for Sockets
• Single Rank SODIMM: Up to 2666/3200 MT/s for FPGA Core Speed 2/1
• Dual Rank SODIMM: Up to 2400/2666 MT/s for FPGA Core Speed 2/1

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]]> DE5A Net-DDR4 https://edu-market.net/everything/de5a-net-ddr4/ Thu, 24 Aug 2023 11:18:46 +0000 https://edu-market.net/?post_type=product&p=3986 The DE5a-Net-DDR4 takes advantage of the powerful Intel Arria 10 FPGA to enable higher speed data processing. The board is armed with 16GB DDR4 memory module, running at over 75 Gbps, up to 7.876 GB/s data transfer via PCIe Gen 3 x8 edge between FPGA and host PC, and 4 on-board QSFP+ connectors. The on-board QDRII memory and DDR4 module can obtain lower application latency and higher application throughput, making it an excellent platform to achieve breakthrough performance in data filtering and algorithmic acceleration.

In addition to these offerings, the DE5a-Net-DDR4 fully supports Intel Open VINO™ toolkit to provide optimal Computer Vision and Deep Learning solutions. Our clients' systems can achieve highest computing performance and lowest cost for their AI applications by leveraging the Arria® 10 FPGA on DE5a-Net-DDR4.

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]]> Features of the DE5A Net-DDR4 • FPGA-024:
Intel ® Arria 10 GX FPGA (10AX115N2F45E1SG)
• FPGA Configuration
On-Board USB Blaster II or JTAG header for FPGA programming
Fast passive parallel (FPPx32) configuration via MAX II CPLD and flash memory
• Memory
256MB FLASH
2 Independent DDR4 SODIMM Sockets, up to 16GB 1066MHz or 8GB 1200MHz for each socket
4 Independent 550 MHz QDRII+SRAMs, 18-bits data bus and 72Mbit for each
• Communication and Expansion
Four QSFP+ connectors
PCI Express (PCIe) x8 edge connector (includes Windows PCIe drivers)
One RS422 expansion header
• Others
General user input / output:
4 LEDs
1 Bracket LED Array
2 7-segments
4 push-buttons
2 slide switches
SMA clock input / output
On-Board Clock
50MHz Oscillator
Programmable Clock Generator
System Monitor and Control
Temperature sensor
Power Monitor
Fan control
Power
PCI Express 6-pin power connector, 12V DC Input
PCI Express edge connector power
Mechanical Specification
PCI Express standard height and 3/4-length

Download Datasheet for DE5A Net-DDR4 • FPGA-024

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]]> DE10-Nano Kit https://edu-market.net/everything/de10-nano-kit/ Tue, 08 Aug 2023 08:42:45 +0000 https://edu-market.net/?post_type=product&p=3939 The DE10-Nano Development Kit presents a robust hardware design platform built around the Intel System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The DE10-Nano development board is equipped with high-speed DDR3 memory, analog to digital capabilities, Ethernet networking, and much more that promise many exciting applications.

The post DE10-Nano Kit appeared first on EDU Market.

]]> The DE10-Nano Kit • FPGA-011 board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects.

The following hardware is provided on the board:

FPGA Device

Intel Cyclone® V SE 5CSEBA6U23I7 device (110K LEs).
Serial configuration device – EPCS64 (revision B2 or later).
USB-Blaster II onboard for programming; JTAG Mode.
HDMI TX, compatible with DVI 1.0 and HDCP v1.4.
2 push-buttons.
4 slide switches.
8 green user LEDs.
Three 50MHz clock sources from the clock generator.
Two 40-pin expansion headers.
One Arduino expansion header (Uno R3 compatibility), can be connected with Arduino shields.
One 10-pin Analog input expansion header (shared with Arduino Analog input).
A/D converter, 4-pin SPI interface with FPGA.

HPS (Hard Processor System)

800MHz Dual-core ARM Cortex-A9 processor.
1GB DDR3 SDRAM (32-bit data bus).
1 Gigabit Ethernet PHY with RJ45 connector.
USB OTG Port, USB Micro-AB connector.
Micro SD card socket.
Accelerometer (I2C interface + interrupt).
UART to USB, USB Mini-B connector.
Warm reset button and cold reset button.
One user button and one user LED.
LTC 2×7 expansion header.

Download Datasheet for DE10-Nano Kit • FPGA-011

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]]> DE0-Nano Development and Education Board https://edu-market.net/everything/de0-nano-development-and-education-board/ Tue, 28 Mar 2023 11:10:47 +0000 https://edu-market.net/?post_type=product&p=2312 The DE0-Nano board introduces a compact-sized FPGA development platform suited for prototyping circuit designs such as robots and "portable" projects. The board is designed to be used in the simplest possible implementation targeting the Cyclone IV device up to 22,320 LEs.

The DE0-Nano has a collection of interfaces including two external GPIO headers to extend designs beyond the DE0-Nano board, on-board memory devices including SDRAM and EEPROM for larger data storage and frame buffering, as well as general user peripheral with LEDs and push-buttons.

The advantages of the DE0-Nano board include its size and weight, as well as its ability to be reconfigured without carrying superfluous hardware, setting itself apart from other general purpose development boards. In addition, for mobile designs where portable power is crucial, the DE0-Nano provides designers with three power scheme options including a USB mini-AB port, 2-pin external power header and two DC 5V pins.

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]]> Cyclone® IV EP4CE22F17C6N FPGA

22,320 Logic elements (LEs)
594 Embedded memory (Kbits)
66 Embedded 18 x 18 multipliers
4 General-purpose PLLs
153 Maximum FPGA I/O pins

Configuration Status and Set-Up Elements

On-board USB-Blaster circuit for programming
FPGA Serial Configuration Device (EPCS)

Expansion Header

Two 40-pin Headers (GPIOs) provides 72 3.3V I/O pins
Two 5V power pins, two 3.3V power pins and four ground pins
One 26-pin header provides 16 3.3V digital I/O pins and 8 analog input pins to connect to analog sensors, etc

Memory Devices

32MB SDRAM
2Kb I2C EEPROM

General User Input/Output

8 green LEDs
2 debounced push-buttons
4 dip switches

G-Sensor

ADI ADXL345, 3-axis accelerometer with high resolution (13-bit)

A/D Converter

NS ADC128S022, 8-Channel, 12-bit A/D Converter
50 ksps to 200 ksps

Clock System

On-board 50MHz clock oscillator

Power Supply

USB Type mini-AB port (5V)
Two DC 5V pins of the GPIO headers (5V)
2-pin external power header (3.6-5.7V)

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]]>